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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
D Low Supply-Voltage Range, 1.8 V . . . 3.6 V D Ultralow-Power Consumption:
D Serial Communication Interface (USART),
Functions as Asynchronous UART or Synchronous SPI Interface - Two USARTs (USART0, USART1) -- MSP430x14x(1) Devices - One USART (USART0) -- MSP430x13x Devices Family Members Include: - MSP430F133: 8KB+256B Flash Memory, 256B RAM - MSP430F135: 16KB+256B Flash Memory, 512B RAM - MSP430F147, MSP430F1471: 32KB+256B Flash Memory, 1KB RAM - MSP430F148, MSP430F1481: 48KB+256B Flash Memory, 2KB RAM - MSP430F149, MSP430F1491: 60KB+256B Flash Memory, 2KB RAM Available in 64-Pin Quad Flat Pack (QFP) and 64-pin QFN For Complete Module Descriptions, See the MSP430x1xx Family User's Guide, Literature Number SLAU049
D D D D D D D D
- Active Mode: 280 A at 1 MHz, 2.2V - Standby Mode: 1.6 A - Off Mode (RAM Retention): 0.1 A Five Power-Saving Modes Wake-Up From Standby Mode in less than 6 s 16-Bit RISC Architecture, 125-ns Instruction Cycle Time 12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature 16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers 16-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse
D
D D
The MSP430F14x1 devices are identical to the MSP430F14x devices with the exception that the ADC12 module is not implemented.
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s. The MSP430x13x and the MSP430x14x(1) series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter (not implemented on the MSP430F14x1 devices), one or two universal serial synchronous/asynchronous communication interfaces (USART), and 48 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system. The timers make the configurations ideal for industrial control applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000 - 2004, Texas Instruments Incorporated
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PM) MSP430F133IPM MSP430F135IPM MSP430F147IPM MSP430F1471IPM MSP430F148IPM MSP430F1481IPM MSP430F149IPM MSP430F1491IPM PLASTIC 64-PIN QFP (PAG) PLASTIC 64-PIN QFN (RTD) MSP430F133IRTD MSP430F135IRTD MSP430F147IRTD MSP430F1471IRTD MSP430F148IRTD MSP430F1481IRTD MSP430F149IRTD MSP430F1491IRTD
-40C to 85C
MSP430F133IPAG MSP430F135IPAG MSP430F147IPAG MSP430F148IPAG MSP430F149IPAG
pin designation, MSP430F133, MSP430F135
PM, PAG, RTD PACKAGE (TOP VIEW)
AVCC DVSS AV SS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 VREF+ XIN XOUT VeREF+ VREF-/VeREF- P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P5.6/ACLK P5.5/SMCLK P5.4/MCLK P5.3 P5.2 P5.1 P5.0 P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/URXD0
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2
P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6/ADC12CLK P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
pin designation, MSP430F147, MSP430F148, MSP430F149
PM, PAG, RTD PACKAGE (TOP VIEW)
AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 VREF+ XIN XOUT VeREF+ VREF-/VeREF- P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P5.6/ACLK P5.5/SMCLK P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6/ADC12CLK P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
pin designation, MSP430F1471, MSP430F1481, MSP430F1491
PM, RTD PACKAGE (TOP VIEW)
AVCC DVSS AVSS P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH DVCC P6.3 P6.4 P6.5 P6.6 P6.7 Reserved XIN XOUT DVSS DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P5.6/ACLK P5.5/SMCLK P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4
P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6 P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
functional block diagrams
MSP430x13x
XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6
8 ROSC XT2IN XT2OUT Oscillator System Clock ACLK SMCLK 16KB Flash 8KB Flash 512B RAM 256B RAM ADC12 12-Bit 8 Channels <10s Conv.
8
8 I/O Port 3/4 16 I/Os
8
8
8
I/O Port 1/2 16 I/Os, with Interrupt Capability
I/O Port 5/6 16 I/Os
MCLK MAB, 4 Bit MCB Emulation Module
Test JTAG CPU Incl. 16 Reg.
MAB,MAB, 16-Bit 16 Bit
MDB, 16-Bit MDB, 16 Bit
Bus Conv
MDB, 8 Bit
4 TMS TCK TDI/TCLK TDO/TDI Watchdog Timer 15/16-Bit Timer_B3 3 CC Reg Shadow Reg Timer_A3 3 CC Reg POR Comparator A USART0 UART Mode SPI Mode
MSP430x14x
XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6
8 ROSC XT2IN XT2OUT Oscillator System Clock ACLK 60KB Flash 2KB RAM 2KB RAM 1KB RAM ADC12 12-Bit 8 Channels <10s Conv.
8
8 I/O Port 3/4 16 I/Os
8
8
8
SMCLK 48KB Flash 32KB Flash
I/O Port 1/2 16 I/Os, with Interrupt Capability
I/O Port 5/6 16 I/Os
MCLK MAB, 4 Bit MCB Emulation Module
Test JTAG CPU Incl. 16 Reg.
MAB,MAB, 16-Bit 16 Bit
MDB, 16-Bit MDB, 16 Bit
Bus Conv
MDB, 8 Bit
4 TMS TCK TDI/TCLK TDO/TDI Hardware Multiplier MPY, MPYS MAC,MACS
Watchdog Timer 15/16-Bit
Timer_B7 7 CC Reg Shadow Reg
Timer_A3 3 CC Reg
POR
Comparator A
USART0 UART Mode SPI Mode
USART1 UART Mode SPI Mode
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
functional block diagrams (continued)
MSP430x14x1
XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6
8 ROSC XT2IN XT2OUT Oscillator System Clock ACLK 60KB Flash 2KB RAM 2KB RAM 1KB RAM
8
8 I/O Port 3/4 16 I/Os
8
8
8
SMCLK 48KB Flash 32KB Flash
I/O Port 1/2 16 I/Os, with Interrupt Capability
I/O Port 5/6 16 I/Os
MCLK MAB, 4 Bit MCB Emulation Module
Test JTAG CPU Incl. 16 Reg.
MAB,MAB, 16-Bit 16 Bit
MDB, 16-Bit MDB, 16 Bit
Bus Conv
MDB, 8 Bit
4 TMS TCK TDI/TCLK TDO/TDI Hardware Multiplier MPY, MPYS MAC,MACS
Watchdog Timer 15/16-Bit
Timer_B7 7 CC Reg Shadow Reg
Timer_A3 3 CC Reg
POR
Comparator A
USART0 UART Mode SPI Mode
USART1 UART Mode SPI Mode
6
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
Terminal Functions MSP430x13x, MSP430x14x
TERMINAL NAME AVCC AVSS DVCC DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6/ADC12CLK P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 P3.5/URXD0 P3.6/UTXD1 P3.7/URXD1 P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 P4.6/TB6 P4.7/TBCLK P5.0/STE1 P5.1/SIMO1 P5.2/SOMI1 P5.3/UCLK1 P5.4/MCLK P5.5/SMCLK 14x devices only NO. 64 62 1 63 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION Analog supply voltage, positive terminal. Supplies the analog portion of the analog-to-digital converter. Analog supply voltage, negative terminal. Supplies the analog portion of the analog-to-digital converter. Digital supply voltage, positive terminal. Supplies all digital parts. Digital supply voltage, negative terminal. Supplies all digital parts. General-purpose digital I/O pin/Timer_A, clock signal TACLK input General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin/SMCLK signal output General-purpose digital I/O pin/Timer_A, compare: Out0 output General-purpose digital I/O pin/Timer_A, compare: Out1 output General-purpose digital I/O pin/Timer_A, compare: Out2 output/ General-purpose digital I/O pin/ACLK output General-purpose digital I/O pin/Timer_A, clock signal at INCLK General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency General-purpose digital I/O pin/conversion clock - 12-bit ADC General-purpose digital I/O pin/Timer_A, compare: Out0 output General-purpose digital I/O pin/slave transmit enable - USART0/SPI mode General-purpose digital I/O pin/slave in/master out of USART0/SPI mode General-purpose digital I/O pin/slave out/master in of USART0/SPI mode General-purpose digital I/O/USART0 clock: external input - UART or SPI mode, output - SPI mode General-purpose digital I/O pin/transmit data out - USART0/UART mode General-purpose digital I/O pin/receive data in - USART0/UART mode General-purpose digital I/O pin/transmit data out - USART1/UART mode General-purpose digital I/O pin/receive data in - USART1/UART mode General-purpose digital I/O pin/Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output General-purpose digital I/O pin/Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output General-purpose digital I/O pin/Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output General-purpose digital I/O pin/Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output General-purpose digital I/O pin/Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output General-purpose digital I/O pin/Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output General-purpose digital I/O pin/Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output General-purpose digital I/O pin/Timer_B, clock signal TBCLK input General-purpose digital I/O pin/slave transmit enable - USART1/SPI mode General-purpose digital I/O pin/slave in/master out of USART1/SPI mode General-purpose digital I/O pin/slave out/master in of USART1/SPI mode General-purpose digital I/O pin/USART1 clock: external input - UART or SPI mode, output - SPI mode General-purpose digital I/O pin/main system clock MCLK output General-purpose digital I/O pin/submain system clock SMCLK output
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
Terminal Functions (Continued) MSP430x13x, MSP430x14x (continued)
TERMINAL NAME P5.6/ACLK P5.7/TBOUTH P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 RST/NMI TCK TDI/TCLK TDO/TDI TMS VeREF+ VREF+ VREF-/VeREF- XIN XOUT XT2IN XT2OUT QFN Pad NO. 50 51 59 60 61 2 3 4 5 6 58 57 55 54 56 10 7 11 8 9 53 52 NA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O I I O I I O I O NA DESCRIPTION General-purpose digital I/O pin/auxiliary clock ACLK output General-purpose digital I/O pin/switch all PWM digital output ports to high impedance - Timer_B7: TB0 to TB6 General-purpose digital I/O pin/analog input a0 - 12-bit ADC General-purpose digital I/O pin/analog input a1 - 12-bit ADC General-purpose digital I/O pin/analog input a2 - 12-bit ADC General-purpose digital I/O pin/analog input a3 - 12-bit ADC General-purpose digital I/O pin/analog input a4 - 12-bit ADC General-purpose digital I/O pin/analog input a5 - 12-bit ADC General-purpose digital I/O pin/analog input a6 - 12-bit ADC General-purpose digital I/O pin/analog input a7 - 12-bit ADC Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash devices). Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. Test data output port. TDO/TDI data output or programming data input terminal Test mode select. TMS is used as an input port for device programming and test. Input for an external reference voltage to the ADC Output of positive terminal of the reference voltage in the ADC Negative terminal for the ADC's reference voltage for both sources, the internal reference voltage, or an external applied reference voltage Input port for crystal oscillator XT1. Standard or watch crystals can be connected. Output terminal of crystal oscillator XT1 Input port for crystal oscillator XT2. Only standard crystals can be connected. Output terminal of crystal oscillator XT2 QFN package pad connection to DVSS recommended.
8
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
Terminal Functions MSP430x14x1
TERMINAL NAME AVCC AVSS DVCC DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6 P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 P3.5/URXD0 P3.6/UTXD1 P3.7/URXD1 P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 P4.6/TB6 P4.7/TBCLK P5.0/STE1 P5.1/SIMO1 P5.2/SOMI1 P5.3/UCLK1 P5.4/MCLK P5.5/SMCLK NO. 64 62 1 63 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Analog supply voltage, positive terminal. Analog supply voltage, negative terminal. Digital supply voltage, positive terminal. Supplies all digital parts. Digital supply voltage, negative terminal. Supplies all digital parts. General-purpose digital I/O pin/Timer_A, clock signal TACLK input General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin/SMCLK signal output General-purpose digital I/O pin/Timer_A, compare: Out0 output General-purpose digital I/O pin/Timer_A, compare: Out1 output General-purpose digital I/O pin/Timer_A, compare: Out2 output General-purpose digital I/O pin/ACLK output General-purpose digital I/O pin/Timer_A, clock signal at INCLK General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency General-purpose digital I/O pin General-purpose digital I/O pin/Timer_A, compare: Out0 output General-purpose digital I/O pin/slave transmit enable - USART0/SPI mode General-purpose digital I/O pin/slave in/master out of USART0/SPI mode General-purpose digital I/O pin/slave out/master in of USART0/SPI mode General-purpose digital I/O/USART0 clock: external input - UART or SPI mode, output - SPI mode General-purpose digital I/O pin/transmit data out - USART0/UART mode General-purpose digital I/O pin/receive data in - USART0/UART mode General-purpose digital I/O pin/transmit data out - USART1/UART mode General-purpose digital I/O pin/receive data in - USART1/UART mode General-purpose digital I/O pin/Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output General-purpose digital I/O pin/Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output General-purpose digital I/O pin/Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output General-purpose digital I/O pin/Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output General-purpose digital I/O pin/Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output General-purpose digital I/O pin/Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output General-purpose digital I/O pin/Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output General-purpose digital I/O pin/Timer_B, clock signal TBCLK input General-purpose digital I/O pin/slave transmit enable - USART1/SPI mode General-purpose digital I/O pin/slave in/master out of USART1/SPI mode General-purpose digital I/O pin/slave out/master in of USART1/SPI mode General-purpose digital I/O pin/USART1 clock: external input - UART or SPI mode, output - SPI mode General-purpose digital I/O pin/main system clock MCLK output General-purpose digital I/O pin/submain system clock SMCLK output DESCRIPTION
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
Terminal Functions (Continued) MSP430x14x1 (continued)
TERMINAL NAME P5.6/ACLK P5.7/TBOUTH P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 RST/NMI TCK TDI/TCLK TDO/TDI TMS DVSS Reserved DVSS XIN XOUT XT2IN XT2OUT QFN Pad NO. 50 51 59 60 61 2 3 4 5 6 58 57 55 54 56 10 7 11 8 9 53 52 NA I I O I O NA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O I I DESCRIPTION General-purpose digital I/O pin/auxiliary clock ACLK output General-purpose digital I/O pin/switch all PWM digital output ports to high impedance - Timer_B7: TB0 to TB6 General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash devices). Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. Test data output port. TDO/TDI data output or programming data input terminal Test mode select. TMS is used as an input port for device programming and test. Connect to DVSS Reserved, do not connect externally Connect to DVSS Input port for crystal oscillator XT1. Standard or watch crystals can be connected. Output terminal of crystal oscillator XT1 Input port for crystal oscillator XT2. Only standard crystals can be connected. Output terminal of crystal oscillator XT2 QFN package pad connection to DVSS recommended.
10
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
short-form description
CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Table 1. Instruction Word Formats
Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g. ADD R4,R5 e.g. CALL e.g. JNE R8 R4 + R5 ---> R5 PC -->(TOS), R8--> PC Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate NOTE: S = source SD FF FF FF FF F F F D = destination SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 --> R11 M(2+R5)--> M(6+R6) M(EDE) --> M(TONI) M(MEM) --> M(TCDAT) M(R10) --> M(Tab+R6) M(R10) --> R11 R10 + 2--> R10 #45 --> M(TONI)
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operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software:
D Active mode AM;
- All clocks are active
D Low-power mode 0 (LPM0);
- CPU is disabled ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
- CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO's dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
- CPU is disabled MCLK and SMCLK are disabled DCO's dc-generator remains enabled ACLK remains active
D Low-power mode 3 (LPM3);
- CPU is disabled MCLK and SMCLK are disabled DCO's dc-generator is disabled ACLK remains active
D Low-power mode 4 (LPM4);
- CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO's dc-generator is disabled Crystal oscillator is stopped
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interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh - 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE Power-up External Reset Watchdog Flash memory NMI Oscillator Fault Flash memory access violation Timer_B7 (see Note 5) Timer_B7 (see Note 5) Comparator_A Watchdog timer USART0 receive USART0 transmit ADC12 (see Note 6) Timer_A3 Timer_A3 INTERRUPT FLAG WDTIFG KEYV (see Note 1) NMIIFG (see Notes 1 & 4) OFIFG (see Notes 1 & 4) ACCVIFG (see Notes 1 & 4) TBCCR0 CCIFG (see Note 2) TBCCR1 to 6 CCIFGs, TBIFG (see Notes 1 & 2) CAIFG WDTIFG URXIFG0 UTXIFG0 ADC12IFG (see Notes 1 & 2) TACCR0 CCIFG (see Note 2) TACCR1 CCIFG, TACCR2 CCIFG, TAIFG (see Notes 1 & 2) P1IFG.0 to P1IFG.7 (see Notes 1 & 2) URXIFG1 UTXIFG1 P2IFG.0 to P2IFG.7 (see Notes 1 & 2) Maskable SYSTEM INTERRUPT Reset WORD ADDRESS 0FFFEh PRIORITY 15, highest
(Non)maskable (Non)maskable (Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable
0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh
14 13 12 11 10 9 8 7 6 5
I/O port P1 (eight flags) USART1 receive USART1 transmit I/O port P2 (eight flags)
Maskable Maskable
0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h
4 3 2 1 0, lowest
NOTES: 1. 2. 3. 4.
Multiple source flags Interrupt flags are located in the module. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. 5. Timer_B7 in MSP430x14x(1) family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interrupt flags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs. 6. ADC12 is not implemented on the 14x1 devices.
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special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
interrupt enable 1 and 2
Address 0h 7 UTXIE0 rw-0 6 URXIE0 rw-0 5 ACCVIE rw-0 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0
WDTIE: OFIE: NMIIE: ACCVIE: URXIE0: UTXIE0:
Address 01h 7
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable Flash access violation interrupt enable USART0: UART and SPI receive-interrupt enable USART0: UART and SPI transmit-interrupt enable
6 5 UTXIE1 rw-0 4 URXIE1 rw-0 3 2 1 0
URXIE1: UTXIE1:
USART1: UART and SPI receive-interrupt enable USART1: UART and SPI transmit-interrupt enable
interrupt flag register 1 and 2
Address 02h 7 UTXIFG0 rw-1 6 URXIFG0 rw-0 5 4 NMIIFG rw-0 3 2 1 OFIFG rw-1 0 WDTIFG rw-(0)
WDTIFG: OFIFG: NMIIFG: URXIFG0: UTXIFG0:
Address 03h 7
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power up or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI pin USART0: UART and SPI receive flag USART0: UART and SPI transmit flag
6 5 UTXIFG1 rw-1 4 URXIFG1 rw-0 3 2 1 0
URXIFG1: UTXIFG1:
USART1: UART and SPI receive flag USART1: UART and SPI transmit flag
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module enable registers 1 and 2
Address 04h 7 UTXE0 rw-0 6 URXE0 USPIE0 rw-0 5 4 3 2 1 0
URXE0: UTXE0: USPIE0:
Address 05h 7
USART0: UART receive enable USART0: UART transmit enable USART0: SPI (synchronous peripheral interface) transmit and receive enable
6 5 UTXE1 rw-0 4 URXE1 USPIE1 rw-0 3 2 1 0
URXE1: UTXE1: USPIE1:
Legend: rw: rw-0:
USART1: UART receive enable USART1: UART transmit enable USART1: SPI (synchronous peripheral interface) transmit and receive enable
Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device
memory organization
MSP430F133 Memory Main: interrupt vector Main: code memory Information memory Boot memory RAM Peripherals Size Flash Flash Size Flash Size ROM Size 16-bit 8-bit 8-bit SFR 8KB 0FFFFh - 0FFE0h 0FFFFh - 0E000h 256 Byte 010FFh - 01000h 1KB 0FFFh - 0C00h 256 Byte 02FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F135 16KB 0FFFFh - 0FFE0h 0FFFFh - 0C000h 256 Byte 010FFh - 01000h 1KB 0FFFh - 0C00h 512 Byte 03FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F147 MSP430F1471 32KB 0FFFFh - 0FFE0h 0FFFFh - 08000h 256 Byte 010FFh - 01000h 1KB 0FFFh - 0C00h 1KB 05FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F148 MSP430F1481 48KB 0FFFFh - 0FFE0h 0FFFFh - 04000h 256 Byte 010FFh - 01000h 1KB 0FFFh - 0C00h 2KB 09FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F149 MSP430F1491 60KB 0FFFFh - 0FFE0h 0FFFFh - 01100h 256 Byte 010FFh - 01000h 1KB 0FFFh - 0C00h 2KB 09FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
BSL Function Data Transmit Data Receive PM, PAG & RTD Package Pins 13 - P1.1 22 - P2.2
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0-n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
8 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 16 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 32 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 48 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 60 KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh Segment 0 w/ Interrupt Vectors Segment 1
Segment 2
Main Memory
0E400h 0E3FFh 0E200h 0E1FFh 0E000h 010FFh 01080h 0107Fh 01000h
0C400h 0C3FFh 0C200h 0C1FFh 0C000h 010FFh 01080h 0107Fh 01000h
08400h 083FFh 08200h 081FFh 08000h 010FFh 01080h 0107Fh 01000h
04400h 043FFh 04200h 041FFh 04000h 010FFh 01080h 0107Fh 01000h
01400h 013FFh Segment n-1 01200h 011FFh Segment n 01100h 010FFh Segment A 01080h 0107Fh Segment B 01000h Information Memory
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User's Guide, literature number SLAU049.
digital I/O
There are six 8-bit I/O ports implemented--ports P1 through P6:
D D D D
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. Read/write access to port-control registers is supported by all instructions.
oscillator and system clock
The clock system in the MSP430x13x and MSP43x14x(1) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
hardware multiplier (MSP430x14x and MSP430x14x1 Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16, 16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.
USART0
The MSP430x13x and the MSP430x14x(1) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
USART1 (MSP430x14x and MSP430x14x1 Only)
The MSP430x14x(1) has a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. Operation of USART1 is identical to USART0.
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comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.
ADC12 (Not implemented in the MSP430x14x1)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_A3 Signal Connections Input Pin Number 12 - P1.0 Device Input Signal TACLK ACLK SMCLK 21 - P2.1 13 - P1.1 22 - P2.2 TAINCLK TA0 TA0 DVSS DVCC 14 - P1.2 TA1 CAOUT (internal) DVSS DVCC 15 - P1.3 TA2 ACLK (internal) DVSS DVCC Module Input Name TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 CCR1 TA1 CCR0 TA0 13 - P1.1 17 - P1.5 27 - P2.7 14 - P1.2 18 - P1.6 23 - P2.3 ADC12 (internal) 15 - P1.3 19 - P1.7 24 - P2.4 Timer NA Module Block Module Output Signal Output Pin Number
timer_B3 (MSP430x13x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
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timer_B7 (MSP430x14x and MSP430x14x1 Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_B3/B7 Signal Connections Input Pin Number 43 - P4.7 Device Input Signal TBCLK ACLK SMCLK 43 - P4.7 36 - P4.0 36 - P4.0 TBCLK TB0 TB0 DVSS DVCC 37 - P4.1 37 - P4.1 TB1 TB1 DVSS DVCC 38 - P4.2 38 - P4.2 TB2 TB2 DVSS DVCC 39 - P4.3 39 - P4.3 TB3 TB3 DVSS DVCC 40 - P4.4 40 - P4.4 TB4 TB4 DVSS DVCC 41 - P4.5 41 - P4.5 TB5 TB5 DVSS DVCC 42 - P4.6 TB6 ACLK (internal) DVSS DVCC Module Input Name TBCLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCI3A CCI3B GND VCC CCI4A CCI4B GND VCC CCI5A CCI5B GND VCC CCI6A CCI6B GND VCC CCR6 TB6 CCR5 TB5 CCR4 TB4 CCR3 TB3 CCR2 TB2 CCR1 TB1 CCR0 TB0 36 - P4.0 ADC12 (internal) Timer NA Module Block Module Output Signal Output Pin Number
37 - P4.1 ADC12 (internal)
38 - P4.2
39 - P4.3
40 - P4.4
41 - P4.5
42 - P4.6
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
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peripheral file map
PERIPHERALS WITH WORD ACCESS Watchdog Timer_B7/ Timer_B3 (see Note 1) Watchdog Timer control Timer_B interrupt vector Timer_B control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Capture/compare control 3 Capture/compare control 4 Capture/compare control 5 Capture/compare control 6 Timer_B register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Capture/compare register 3 Capture/compare register 4 Capture/compare register 5 Capture/compare register 6 Timer_A3 Timer_A interrupt vector Timer_A control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Reserved Reserved Reserved Reserved Timer_A register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Reserved Reserved Reserved Reserved Hardware Multiplier (MSP430x14x and MSP430x14x1 only) Sum extend Result high word Result low word Second operand Multiply signed +accumulate/operand1 Multiply+accumulate/operand1 Multiply signed/operand1 Multiply unsigned/operand1 SUMEXT RESHI RESLO OP2 MACS MAC MPYS MPY TAR TACCR0 TACCR1 TACCR2 WDTCTL TBIV TBCTL TBCCTL0 TBCCTL1 TBCCTL2 TBCCTL3 TBCCTL4 TBCCTL5 TBCCTL6 TBR TBCCR0 TBCCR1 TBCCR2 TBCCR3 TBCCR4 TBCCR5 TBCCR6 TAIV TACTL TACCTL0 TACCTL1 TACCTL2 0120h 011Eh 0180h 0182h 0184h 0186h 0188h 018Ah 018Ch 018Eh 0190h 0192h 0194h 0196h 0198h 019Ah 019Ch 019Eh 012Eh 0160h 0162h 0164h 0166h 0168h 016Ah 016Ch 016Eh 0170h 0172h 0174h 0176h 0178h 017Ah 017Ch 017Eh 013Eh 013Ch 013Ah 0138h 0136h 0134h 0132h 0130h
NOTE 1: Timer_B7 in MSP430x14x(1) family has 7 CCRs, Timer_B3 in MSP430x13x family has 3 CCRs.
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peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED) Flash Flash control 3 Flash control 2 Flash control 1 ADC12 Conversion memory 15 (Not implemented in Conversion memory 14 the MSP430x14x1) Conversion memory 13 Conversion memory 12 Conversion memory 11 Conversion memory 10 Conversion memory 9 Conversion memory 8 Conversion memory 7 Conversion memory 6 Conversion memory 5 Conversion memory 4 Conversion memory 3 Conversion memory 2 Conversion memory 1 Conversion memory 0 Interrupt-vector-word register Inerrupt-enable register Inerrupt-flag register Control register 1 Control register 0 ADC memory-control register15 ADC memory-control register14 ADC memory-control register13 ADC memory-control register12 ADC memory-control register11 ADC memory-control register10 ADC memory-control register9 ADC memory-control register8 ADC memory-control register7 ADC memory-control register6 ADC memory-control register5 ADC memory-control register4 ADC memory-control register3 ADC memory-control register2 ADC memory-control register1 ADC memory-control register0 FCTL3 FCTL2 FCTL1 ADC12MEM15 ADC12MEM14 ADC12MEM13 ADC12MEM12 ADC12MEM11 ADC12MEM10 ADC12MEM9 ADC12MEM8 ADC12MEM7 ADC12MEM6 ADC12MEM5 ADC12MEM4 ADC12MEM3 ADC12MEM2 ADC12MEM1 ADC12MEM0 ADC12IV ADC12IE ADC12IFG ADC12CTL1 ADC12CTL0 ADC12MCTL15 ADC12MCTL14 ADC12MCTL13 ADC12MCTL12 ADC12MCTL11 ADC12MCTL10 ADC12MCTL9 ADC12MCTL8 ADC12MCTL7 ADC12MCTL6 ADC12MCTL5 ADC12MCTL4 ADC12MCTL3 ADC12MCTL2 ADC12MCTL1 ADC12MCTL0 012Ch 012Ah 0128h 015Eh 015Ch 015Ah 0158h 0156h 0154h 0152h 0150h 014Eh 014Ch 014Ah 0148h 0146h 0144h 0142h 0140h 01A8h 01A6h 01A4h 01A2h 01A0h 08Fh 08Eh 08Dh 08Ch 08Bh 08Ah 089h 088h 087h 086h 085h 084h 083h 082h 081h 080h
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS USART1 (MSP430x14x and MSP430x14x1 only) Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control USART0 Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control Comparator_A Comparator_A port disable Comparator_A control2 Comparator_A control1 Basic Clock Basic clock system control2 Basic clock system control1 DCO clock frequency control Port P6 Port P6 selection Port P6 direction Port P6 output Port P6 input Port P5 Port P5 selection Port P5 direction Port P5 output Port P5 input Port P4 Port P4 selection Port P4 direction Port P4 output Port P4 input Port P3 Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input U1TXBUF U1RXBUF U1BR1 U1BR0 U1MCTL U1RCTL U1TCTL U1CTL U0TXBUF U0RXBUF U0BR1 U0BR0 U0MCTL U0RCTL U0TCTL U0CTL CAPD CACTL2 CACTL1 BCSCTL2 BCSCTL1 DCOCTL P6SEL P6DIR P6OUT P6IN P5SEL P5DIR P5OUT P5IN P4SEL P4DIR P4OUT P4IN P3SEL P3DIR P3OUT P3IN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 07Fh 07Eh 07Dh 07Ch 07Bh 07Ah 079h 078h 077h 076h 075h 074h 073h 072h 071h 070h 05Bh 05Ah 059h 058h 057h 056h 037h 036h 035h 034h 033h 032h 031h 030h 01Fh 01Eh 01Dh 01Ch 01Bh 01Ah 019h 018h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt-edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Functions SFR module enable 2 SFR module enable 1 SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN ME2 ME1 IFG2 IFG1 IE2 IE1 026h 025h 024h 023h 022h 021h 020h 005h 004h 003h 002h 001h 000h
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to + 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse.
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23
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
recommended operating conditions
PARAMETER Supply voltage during program execution, VCC (AVCC = DVCC = VCC) Supply voltage during flash memory programming, VCC (AVCC = DVCC = VCC) Supply voltage, VSS (AVSS = DVSS = VSS) Operating free-air temperature range, TA LF selected, XTS=0 LFXT1 crystal frequency, f(LFXT1) (see Notes 1 and 2) XT1 selected, XTS=1 XT1 selected, XTS=1 XT2 crystal frequency, f(XT2) Processor frequency (signal MCLK), f(System) MSP430x13x MSP430x14x(1) Watch crystal Ceramic resonator Crystal Ceramic resonator Crystal VCC = 1.8 V VCC = 3.6 V 450 1000 450 1000 DC DC MSP430F13x, MSP430F14x(1) MSP430F13x, MSP430F14x(1) MIN 1.8 2.7 0.0 -40 32768 8000 8000 8000 8000 4.15 8 MHz kHz NOM MAX 3.6 3.6 0.0 85 UNITS V V V C Hz kHz kHz
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1M resistor from XOUT to VSS is recommended when VCC < 2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at VCC 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at VCC 2.8 V. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f (MHz) Supply voltage range, 'F13x/'F14x(1), during program execution
4.15 MHz
1.8 V
2.7 V 3 V Supply Voltage - V
Figure 1. Frequency vs Supply Voltage, MSP430F13x or MSP430F14x(1)
24
POST OFFICE BOX 655303
IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII
3.6 V
8.0 MHz
Supply voltage range, 'F13x/'F14x(1), during flash memory programming
* DALLAS, TEXAS 75265
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
supply current into AVCC + DVCC excluding external current
PARAMETER Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 4 096 Hz, f(ACLK) = 4,096 Hz XTS=0, SELM=(0,1) XTS=0, SELM=3 Low-power mode, (LPM0) (see Note 1) Low-power mode, (LPM2), f(MCLK) = f (SMCLK) = 0 MHz, f(ACLK) = 32.768 Hz, SCG0 = 0 TEST CONDITIONS VCC = 2.2 V TA = -40C to 85C VCC = 3 V VCC = 2.2 V TA = -40C to 85C VCC = 3 V TA = -40C to 85C VCC = 2.2 V VCC = 3 V VCC = 2.2 V TA = -40C to 85C TA = -40C TA = 25C I(LPM3) Low-power mode, (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 (see Note 2) TA = 85C TA = -40C TA = 25C TA = 85C TA = -40C TA = 25C I(LPM4) Low-power mode, (LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 TA = 85C TA = -40C TA = 25C TA = 85C VCC = 3 V VCC = 3 V VCC = 3 V 9 32 55 11 17 0.8 VCC = 2.2 V 0.9 1.6 1.8 1.6 2.3 0.1 VCC = 2.2 V 0.1 0.8 0.1 0.1 0.8 20 45 70 14 22 1.5 1.5 2.8 2.2 1.9 3.9 0.5 0.5 2.5 0.5 0.5 2.5 A A A A A A A A 420 2.5 560 7 A A MIN NOM 280 MAX 350 A A UNIT
I(AM)
I(AM)
I(LPM0)
I(LPM2)
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. Timer_B is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency, F-version I(AM) = I(AM) [1 MHz] x f(System) [MHz] Current consumption of active mode versus supply voltage, F-version I(AM) = I(AM) [3 V] + 175 A/V x (VCC - 3 V)
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25
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
SCHMITT-trigger inputs - Ports P1, P2, P3, P4, P5, and P6
PARAMETER VIT+ VIT- Vhys Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ - VIT-) TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN 1.1 1.5 0.4 0.90 0.3 0.5 TYP MAX 1.5 1.9 0.9 1.3 1.1 1 V V V UNIT
standard inputs - RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER VIL VIH Low-level input voltage High-level input voltage TEST CONDITIONS VCC = 2.2 V / 3 V MIN VSS 0.8xVCC TYP MAX VSS+0.6 VCC UNIT V V
inputs Px.x, TAx, TBx
PARAMETER TEST CONDITIONS Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag, (see Note 1) TA0, TA1, TA2 t(cap) f(TAext) f(TBext) f(TAint) Timer_A, Timer_B capture timing Timer_A, Timer_B clock frequency externally applied to pin TB0, TB1, TB2, TB3, TB4, TB5, TB6 (see Note 2) TACLK, TBCLK, INCLK: t(H) = t(L) VCC 2.2 V/3 V 2.2 V 3V 2.2 V 3V 2.2 V 3V MIN 1.5 62 50 62 50 8 MHz 10 ns ns TYP MAX UNIT cycle
t(int)
External interrupt timing
2.2 V 8 Timer_A, Timer_B clock SMCLK or ACLK signal selected MHz frequency f(TBint) 3V 10 NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. 2. Seven capture/compare registers in 'x14x(1) and three capture/compare registers in 'x13x.
leakage current (see Note 1)
PARAMETER Ilkg(P1.x) Ilkg(P2.x) Leakage current (see Note 1) Port P1 TEST CONDITIONS V(P1.x) (see Note 2) V(P2.3) V(P2.4) (see Note 2) MIN TYP MAX 50 nA UNIT
VCC = 2.2 V/3 V Port P2 50 Ilkg(P6.x) Port P6 V(P6.x) (see Note 2) 50 NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
26
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
outputs - Ports P1, P2, P3, P4, P5, and P6
PARAMETER TEST CONDITIONS IOH(max) = -1 mA, IOH(max) = -6 mA, IOH(max) = -1 mA, IOH(max) = -6 mA, IOL(max) = 1.5 mA, IOL(max) = 6 mA, IOL(max) = 1.5 mA, IOL(max) = 6 mA, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 MIN VCC-0.25 VCC-0.6 VCC-0.25 VCC-0.6 VSS VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS+0.25 VSS+0.6 VSS+0.25 VSS+0.6 UNIT
VOH
High-level output voltage
V
VOL
Low-level output voltage
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 6 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 24 mA to satisfy the maximum specified voltage drop.
output frequency
PARAMETER fTAx fACLK, fMCLK, fSMCLK TA0..2, TB0-TB6, Internal clock source, SMCLK signal applied (see Note 1) P5.6/ACLK, P5.4/MCLK, P5.5/SMCLK CL = 20 pF TEST CONDITIONS MIN DC TYP MAX fSystem MHz CL = 20 pF P2.0/ACLK CL = 20 pF, VCC = 2.2 V / 3 V tXdc Duty cycle of output frequency, P1.4/SMCLK, CL = 20 pF, VCC = 2.2 V / 3 V fACLK = fLFXT1 = fXT1 fACLK = fLFXT1 = fLF fACLK = fLFXT1/n fSMCLK = fLFXT1 = fXT1 fSMCLK = fLFXT1 = fLF fSMCLK = fLFXT1/n fSMCLK = fDCOCLK 40% 30% 50% 40% 35% 50%- 15 ns 50%- 15 ns 50% 50% 60% 65% 50%- 15 ns 50%- 15 ns fSystem 60% 70% UNIT
NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK frequencies can be different.
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
outputs - Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
16 I OL - Low-Level Output Current - mA I OL - Low-Level Output Current - mA 14 12 10 8 6 4 2 0 0.0 VCC = 2.2 V P2.7 TA = 25C 20 TA = 85C 25 VCC = 3 V P2.7 TA = 25C
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
TA = 85C
15
10
5
0.5
1.0
1.5
2.0
2.5
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL - Low-Level Output Voltage - V
VOL - Low-Level Output Voltage - V
Figure 2
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
0 I OH - High-Level Output Current - mA -2 -4 -6 -8 -10 TA = 85C -12 TA = 25C -14 0.0 0.5 1.0 1.5 2.0 2.5 -30 0.0 0.5 VCC = 2.2 V P2.7 I OH - High-Level Output Current - mA 0 VCC = 3 V P2.7 -5
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
-10
-15
-20
TA = 85C
-25
TA = 25C
1.0
1.5
2.0
2.5
3.0
3.5
VOH - High-Level Output Voltage - V
VOH - High-Level Output Voltage - V
Figure 4
Figure 5
28
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS f = 1 MHz t(LPM3) Delay time f = 2 MHz f = 3 MHz VCC = 2.2 V/3 V MIN TYP MAX 6 6 6 s UNIT
RAM
PARAMETER VRAMh TEST CONDITIONS CPU HALTED (see Note 1) MIN 1.6 TYP MAX UNIT V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition.
Comparator_A (see Note 1)
PARAMETER I(DD) TEST CONDITIONS CAON=1, CARSEL=0, CAREF=0 CAON=1, CARSEL=0, CAREF=1/2/3, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 CAON =1 node PCA0=1, CARSEL=1, CAREF=1, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 PCA0=1, CARSEL=1, CAREF=2, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 PCA0=1, CARSEL=1, CAREF=3, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 TA = 85C See Note 2 CAON=1 TA = 25C, Overdrive 10 mV, 25 C, Without filter: CAF=0 t(response LH) TA = 25C, Overdrive 10 mV, 25 C, With filter: CAF=1 TA = 25C, Overdrive 10 mV, 25 C, Without filter: CAF=0 t(response HL) TA = 25C, Overdrive 10 mV, 25 C, With filter: CAF=1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V 0 MIN TYP 25 45 30 45 MAX 40 60 50 71 VCC-1 0.24 0.25 UNIT A A V
I(Refladder/Refdiode) V(IC) V(Ref025) Common-mode input voltage Voltage @ 0.25 V V CC CC node CC
0.23
V(Ref050)
Voltage @ 0.5V V CC
VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V
0.47 390 400 -30 0 130 80 1.4 0.9 130 80 1.4 0.9
0.48 480 490
0.5 540 mV 550 30 mV mV ns s ns s
V(RefVT) V(offset) Vhys
(see Figure 6) Offset voltage Input hysteresis
0.7 210 150 1.9 1.5 210 150 1.9 1.5
1.4 300 240 3.4 2.6 300 240 3.4 2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
650 VCC = 3 V V(REFVT) - Reference Volts -mV V(REFVT) - Reference Volts -mV 600 Typical 550 600 Typical 550 650 VCC = 2.2 V
500
500
450
450
400 -45
-25
-5
15
35
55
75
95
400 -45
-25
-5
15
35
55
75
95
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 6. V(RefVT) vs Temperature, VCC = 3 V
0 V VCC 0 1 CAON
Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V
CAF
Low Pass Filter + _ 0 1 0 1
To Internal Modules
V+ V-
CAOUT Set CAIFG Flag 2.0 s
Figure 8. Block Diagram of Comparator_A Module
Overdrive V-
VCAOUT
400 mV V+ t(response)
Figure 9. Overdrive Definition
30
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
PUC/POR
PARAMETER t(POR_Delay) VPOR Internal time delay to release POR VCC threshold at which POR release delay time begins (see Note 1) VCC threshold required to generate a POR (see Note 2) TA = -40C TA = 25C TA = 85C VCC |dV/dt| 1V/ms VCC = 2.2 V/3 V 1.4 1.1 0.8 0.2 TEST CONDITIONS MIN TYP 150 MAX 250 1.8 1.5 1.2 UNIT s V V V V
V(min)
t(reset) RST/NMI low time for PUC/POR Reset is accepted internally 2 s NOTES: 1. VCC rise time dV/dt 1V/ms. 2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less than -1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms. V VCC
V
POR POR No POR POR
V (min)
t
Figure 10. Power-On Reset (POR) vs Supply Voltage
2 1.8 1.6 V POR - V 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 TA - Temperature - C 25C 0.8 1.2 1.4 1.8 1.5 1.2
Figure 11. VPOR vs Temperature
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31
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
DCO (see Note 1)
PARAMETER f(DCO03) f(DCO13) f(DCO23) f(DCO33) f(DCO43) f(DCO53) f(DCO63) f(DCO73) f(DCO47) f(DCO77) S(Rsel) S(DCO) Dt DV TEST CONDITIONS Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25C VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V MIN 0.08 0.08 0.14 0.14 0.22 0.22 0.37 0.37 0.61 0.61 1 1 1.6 1.69 2.4 2.7 fDCO40 x 1.7 4 4.4 1.35 1.07 -0.31 -0.33 0 NOM 0.12 0.13 0.19 0.18 0.30 0.28 0.49 0.47 0.77 0.75 1.2 1.3 1.9 2.0 2.9 3.2 fDCO40 x 2.1 4.5 4.9 1.65 1.12 -0.36 -0.38 5 MAX 0.15 0.16 0.23 0.22 0.36 0.34 0.59 0.56 0.93 0.90 1.5 1.5 2.2 2.29 3.4 3.65 fDCO40 x 2.5 4.9 5.4 2 1.16 -0.40 -0.43 10 %/C %/V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz UNIT
Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25C Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25C SR = fRsel+1 / fRsel SDCO = fDCO+1 / fDCO Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 2) Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 2)
NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System). 2. This parameter is not production tested. 1 f DCOCLK
Frequency Variance
2.2
32
IIIIIII IIIIIII
3
Max f DCO_0 Min
IIIIIII IIIIIII
VCC - V
Max f DCO_7 Min
0
1
2
3
4
5
6
7
DCO
Figure 12. DCO Characteristics
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
main DCO characteristics D Individual devices have a minimum and maximum operation frequency. The specified parameters for fDCOx0 to fDCOx7 are valid for all devices. D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps with Rsel1, ... Rsel6 overlaps with Rsel7. D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO. D Modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to f(DCO) x (2MOD/32 ). DCO when using ROSC (see Note 1)
PARAMETER fDCO, DCO output frequency Dt, Temperature drift TEST CONDITIONS Rsel = 4, DCO = 3, MOD = 0, DCOR = 1, TA = 25C Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 VCC 2.2 V 3V 2.2 V/3 V MIN NOM 1.815% 1.9515% 0.1 10 MAX UNIT MHz MHz %/C %/V
Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V NOTES: 1. ROSC = 100k. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = 50ppm/C.
crystal oscillator, LFXT1 oscillator (see Note 1)
PARAMETER TEST CONDITIONS XTS=0; LF oscillator selected VCC = 2.2 V/3 V XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V XTS=0; LF oscillator selected VCC = 2.2 V/3 V XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V VCC = 2.2 V/3 V (see Note 2) VSS 0.8 x VCC MIN NOM 12 pF 2 12 pF 2 0.2 x VCC VCC V V MAX UNIT
CXIN
Integrated input capacitance
CXOUT
Integrated output capacitance
VIL VIH
Input levels at XIN
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER CXT2IN CXT2OUT VIL VIH Input capacitance Output capacitance Input levels at XT2IN TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V (see Note 2) VSS 0.8 x VCC MIN NOM 2 2 0.2 x VCC VCC MAX UNIT pF pF V V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0, USART1 (see Note 1)
PARAMETER t() () USART0/1: deglitch time VCC = 2.2 V VCC = 3 V TEST CONDITIONS MIN 200 150 NOM 430 280 MAX 800 500 UNIT ns
NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t() to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0/1 line.
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER AVCC Analog supply voltage TEST CONDITIONS AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V All P6.0/A0 to P6.7/A7 terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x=1 0 x 7; V(AVSS) VP6.x/Ax V(AVCC) fADC12CLK = 5.0 MHz ADC12ON = 1, REFON = 0 SHT0=0, SHT1=0, ADC12DIV=0 fADC12CLK = 5.0 MHz ADC12ON = 0, REFON = 1, REF2_5V = 1 fADC12CLK = 5.0 MHz ADC12ON = 0, REFON = 1, REF2_5V = 0 Only one terminal can be selected at one time, P6.x/Ax 2.2 V 3V 3V 2.2 V 3V 2.2 V MIN 2.2 NOM MAX 3.6 UNIT V
V(P6.x/Ax)
Analog input voltage range (see Note 2) Operating supply current into AVCC terminal (see Note 3)
0 0.65 0.8 0.5 0.5 0.5
VAVCC 1.3
V
IADC12
mA 1.6 0.8 0.8 mA 0.8 40 pF mA
IREF+
Operating supply current into AVCC terminal (see Note 4)
CI
Input capacitance
RI Input MUX ON resistance 0V VAx VAVCC 3V 2000 Not production tested, limits verified by design NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. 3. The internal reference supply current is not included in current consumption parameter IADC12. 4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER VeREF+ VREF- /VeREF- (VeREF+ - VREF-/VeREF-) IVeREF+ IVREF-/VeREF- Positive external reference voltage input Negative external reference voltage input Differential external reference voltage input Static input current TEST CONDITIONS VeREF+ > VREF-/VeREF- (see Note 2) VeREF+ > VREF-/VeREF- (see Note 3) VeREF+ > VREF-/VeREF- (see Note 4) 0V VeREF+ VAVCC 2.2 V/3 V MIN 1.4 0 1.4 NOM MAX VAVCC 1.2 VAVCC 1 UNIT V V V A
Static input current 0V VeREF- VAVCC 2.2 V/3 V 1 A NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.
34
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
12-bit ADC, built-in reference
PARAMETER Positive built-in reference voltage output TEST CONDITIONS REF2_5V = 1 for 2.5 V IVREF+ IVREF+max REF2_5V = 0 for 1.5 V IVREF+ IVREF+max REF2_5V = 0, IVREF+ 1mA REF2_5V = 1, IVREF+ 0.5mA REF2_5V = 1, IVREF+ 1mA 2.2 V 3V IVREF+ = 500 A +/- 100 A Analog input voltage ~0.75 V; REF2_5V = 0 IVREF+ = 500 A 100 A Analog input voltage ~1.25 V; REF2_5V = 1 IVREF+ =100 A 900 A, CVREF+=5 F, ax ~0.5 x VREF+ Error of conversion result 1 LSB REFON =1, 0 mA IVREF+ IVREF+max IVREF+ is a constant in the range of 0 mA IVREF+ 1 mA IVREF+ = 0.5 mA, CVREF+ = 10 F, VREF+ = 1.5 V, VAVCC = 2.2 V 2.2 V 3V 3V 3V 2.2 V/3 V MIN 2.4 1.44 2.2
VREF+ + 0.15 VREF+ + 0.15
NOM 2.5 1.5
MAX 2.6
UNIT
VREF+
V 1.56
AVCC(min)
AVCC minimum voltage, Positive built-in reference active Load current out of VREF+ terminal
V -0.5 -1 2 2 2 LSB mA
0.01
IVREF+
IL(VREF)+
Load-current regulation VREF+ terminal
LSB
IDL(VREF) + CVREF+ TREF+ tREFON
Load current regulation VREF+ terminal Capacitance at pin VREF+ (see Note 1) Temperature coefficient of built-in reference Settle time of internal reference voltage (see Figure 13 and Note 2)
3V
20
ns F
2.2 V/3 V 2.2 V/3 V
5
10 100
ppm/C
17
ms
Not production tested, limits characterized Not production tested, limits verified by design NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF-/VeREF- and AVSS: 10 F tantalum and 100 nF ceramic. NOTES: 2. The condition is that the error in a conversion started after tREFON is less than 0.5 LSB. The settling time depends on the external capacitive load. CVREF+ 100 F
10 F
tREFON .66 x CVREF+ [ms] with CVREF+ in F
1 F 0 1 ms 10 ms 100 ms tREFON
Figure 13. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
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35
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
From Power Supply
DVCC + - 10 F DVSS 100 nF AVCC AVSS 100 nF VREF+ or VeREF+
+ - 10 F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] + - 10 F + - 10 F 100 nF 100 nF
MSP430F13x MSP430F14x
Apply External Reference
VREF-/VeREF-
Figure 14. Supply Voltage and Reference Voltage Design VREF-/VeREF- External Supply
From Power Supply DVCC + - 10 F DVSS 100 nF AVCC AVSS 100 nF VREF+ or VeREF+
+ - Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 10 F + - 10 F Reference Is Internally Switched to AVSS 100 nF
MSP430F13x MSP430F14x
VREF-/VeREF-
Figure 15. Supply Voltage and Reference Voltage Design VREF-/VeREF- = AVSS, Internally Connected
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POST OFFICE BOX 655303
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
12-bit ADC, timing parameters
PARAMETER fADC12CLK fADC12OSC Internal ADC12 oscillator TEST CONDITIONS For specified performance of ADC12 linearity parameters ADC12DIV=0, fADC12CLK=fADC12OSC CVREF+ 5 F, Internal oscillator, fADC12OSC = 3.7 MHz to 6.3 MHz 2.2V/ 3V 2.2 V/ 3V 2.2 V/ 3V MIN 0.45 3.7 2.06 13xADC12DIVx 1/fADC12CLK 100 3V 2.2 V 1220 ns 1400 NOM 5 MAX 6.3 6.3 3.51 UNIT MHz MHz s s ns
tCONVERT
Conversion time
External fADC12CLK from ACLK, MCLK or SMCLK: ADC12SSEL 0 (see Note 1) RS = 400 , RI = 1000 , CI = 30 pF = [RS + RI] x CI;(see Note 2)
tADC12ON tSample
Turn on settling time of the ADC Sampling time
Not production tested, limits characterized Not production tested, limits verified by design NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than 0.5 LSB. The reference and input signal are already settled. 2. Approximately ten Tau () are needed to get an error of less than 0.5 LSB: tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER EI ED EO EG ET Integral linearity error Differential linearity error Offset error TEST CONDITIONS 1.4 V (VeREF+ - VREF-/VeREF-) min 1.6 V 1.6 V < (VeREF+ - VREF-/VeREF-) min [V(AVCC)] (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), Internal impedance of source RS < 100 , CVREF+ = 10 F (tantalum) and 100 nF (ceramic) (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) 2.2 V/3 V 2.2 V/3 V 2 1.1 2 MIN NOM MAX 2 1.7 1 4 2 5 UNIT LSB LSB
2.2 V/3 V
LSB
Gain error Total unadjusted error
2.2 V/3 V 2.2 V/3 V
LSB LSB
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37
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
PARAMETER ISENSOR VSENSOR TCSENSOR tSENSOR(sample) IVMID VMID tVMID(sample) Sample time required if channel 10 is selected (see Note 2) Current into divider at channel 11 (see Note 3) AVCC divider at channel 11 Sample time required if channel 11 is selected (see Note 4) Operating supply current into AVCC terminal (see Note 1) TEST CONDITIONS REFON = 0, INCH = 0Ah, ADC12ON=NA, TA = 25_C ADC12ON = 1, INCH = 0Ah, TA = 0C ADC12ON = 1, INCH = 0Ah ADC12ON = 1, INCH = 0Ah, Error of conversion result 1 LSB ADC12ON = 1, INCH = 0Bh ADC12ON = 1, INCH = 0Bh, VMID is ~0.5 x VAVCC ADC12ON = 1, INCH = 0Bh, Error of conversion result 1 LSB 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 1400 1220 1.1 1.5 30 30 NA NA 1.10.04 1.500.04 V ns MIN NOM 40 60 986 986 3.55 3.55 MAX 120 160 9865% 9865% 3.553% 3.553% mV/C s s A A mV UNIT A A
Not production tested, limits characterized NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal is high). Therefore it includes the constant current through the sensor and the reference. 2. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on). 3. No additional current is needed. The VMID is used during sampling. 4. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER VCC(PGM/ ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock, 0 tBlock, 1-63 tBlock, End tMass Erase tSeg Erase TEST CONDITIONS VCC MIN NOM MAX UNIT
Program and Erase supply voltage Flash Timing Generator frequency Supply current from DVCC during program Supply current from DVCC during erase Cumulative program time Cumulative mass erase time Program/Erase endurance Data retention duration Word or byte program time Block program time for 1st byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Segment erase time see Note 3 TJ = 25C see Note 1 see Note 2 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V
2.7 257 3 3 200 104 100 35 30 21 6 5297 4819
3.6 476 5 7 4 105
V kHz mA mA ms ms cycles years
tFTG
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
JTAG Interface
PARAMETER fTCK RInternal TCK input frequency Internal pull-up resistance on TMS, TCK, TDI/TCLK TEST CONDITIONS see Note 1 see Note 2 VCC 2.2 V 3V 2.2 V/ 3 V MIN 0 0 25 60 NOM MAX 5 10 90 UNIT MHz MHz k
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
PARAMETER VCC(FB) VFB IFB tFB Supply voltage during fuse-blow condition Voltage level on TDI/TCLK for fuse-blow: F versions Supply current into TDI/TCLK during fuse blow Time to blow fuse TEST CONDITIONS TA = 25C VCC MIN 2.5 6 7 100 1 NOM MAX UNIT V V mA ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode.
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39
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic
port P1, P1.0 to P1.7, input/output with Schmitt-trigger
P1SEL.x P1DIR.x Direction Control From Module 0 1 Pad Logic P1OUT.x Module X OUT 0 1 P1.7/TA2 P1.0/TACLK ..
P1IN.x EN Module X IN P1IRQ.x D P1IE.x Q P1IFG.x EN Set Interrupt Edge Select
Interrupt Flag
P1IES.x P1SEL.x
PnSel.x P1Sel.0 P1Sel.1 P1Sel.2 P1Sel.3 P1Sel.4 P1Sel.5 P1Sel.6 P1Sel.7
PnDIR.x P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3 P1DIR.4 P1DIR.5 P1DIR.6 P1DIR.7
Dir. CONTROL FROM MODULE P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3 P1DIR.4 P1DIR.5 P1DIR.6 P1DIR.7
PnOUT.x P1OUT.0 P1OUT.1 P1OUT.2 P1OUT.3 P1OUT.4 P1OUT.5 P1OUT.6 P1OUT.7
MODULE X OUT DVSS Out0 signal Out1 signal Out2 signal SMCLK Out0 signal Out1 signal Out2 signal
PnIN.x P1IN.0 P1IN.1 P1IN.2 P1IN.3 P1IN.4 P1IN.5 P1IN.6 P1IN.7
MODULE X IN TACLK CCI0A CCI1A CCI2A unused unused unused unused
PnIE.x P1IE.0 P1IE.1 P1IE.2 P1IE.3 P1IE.4 P1IE.5 P1IE.6 P1IE.7
PnIFG.x P1IFG.0 P1IFG.1 P1IFG.2 P1IFG.3 P1IFG.4 P1IFG.5 P1IFG.6 P1IFG.7
PnIES.x P1IES.0 P1IES.1 P1IES.2 P1IES.3 P1IES.4 P1IES.5 P1IES.6 P1IES.7
Signal from or to Timer_A
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT 0 1 0 1 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.6/ADC12CLK P2.7/TA0 Bus Keeper 0: Input 1: Output
Pad Logic P2IN.x EN Module X IN P2IRQ.x D P2IE.x P2IFG.x Q EN Set Interrupt Edge Select P2IES.x P2SEL.x CAPD.X
Interrupt Flag
x: Bit Identifier 0 to 2, 6, and 7 for Port P2 Dir. CONTROL FROM MODULE P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.6
PnSel.x P2Sel.0 P2Sel.1 P2Sel.2 P2Sel.6
PnDIR.x P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.6
PnOUT.x P2OUT.0 P2OUT.1 P2OUT.2 P2OUT.6
MODULE X OUT ACLK DVSS CAOUT ADC12CLK Out0 signal
PnIN.x P2IN.0 P2IN.1 P2IN.2 P2IN.6 P2IN.7
MODULE X IN unused INCLK CCI0B unused unused
PnIE.x P2IE.0 P2IE.1 P2IE.2 P2IE.6 P2IE.7
PnIFG.x P2IFG.0 P2IFG.1 P2IFG.2 P2IFG.6 P2IFG.7
PnIES.x P2IES.0 P2IES.1 P2IES.2 P2IES.6 P2IES.7
P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 Signal from Comparator_A Signal to Timer_A Signal from Timer_A ADC12CLK signal is output of the 12-bit ADC module
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41
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3 P2DIR.3 Direction Control From Module P2OUT.3 Module X OUT 0 1 0 1 0: Input 1: Output Pad Logic P2.3/CA0/TA1
P2IN.3 EN Module X IN P2IRQ.3 D P2IE.3 P2IFG.3 Q EN Set
Interrupt Edge Select
Bus Keeper
CAPD.3 Comparator_A CAEX P2CA CAREF CAF +
Interrupt Flag
P2IES.3 P2SEL.3
CCI1B To Timer_A3 P2SEL.4 P2IES.4 Interrupt Flag P2IFG.4 P2IRQ.4 Module X IN P2IE.4 D EN P2IN.4 Bus Keeper Q Set EN
Edge Select Interrupt
- CAREF Reference Block
CAPD.4
Module X OUT P2OUT.4 From Module Direction Control P2DIR.4 P2SEL.4 DIRECTION CONTROL FROM MODULE P2DIR.3 P2DIR.4
1 0 1 0 Pad Logic 1: Output 0: Input P2.4/CA1/TA2
PnSel.x P2Sel.3
PnDIR.x P2DIR.3
PnOUT.x P2OUT.3 P2OUT.4
MODULE X OUT Out1 signal Out2 signal
PnIN.x P2IN.3 P2IN.4
MODULE X IN unused unused
PnIE.x P2IE.3 P2IE.4
PnIFG.x P2IFG.3 P2IFG.4
PnIES.x P2IES.3 P2IES.4
P2Sel.4 P2DIR.4 Signal from Timer_A
42
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P2, P2.5, input/output with Schmitt-trigger and Rosc function for the basic clock module
P2SEL.5 P2DIR.5 Direction Control From Module P2OUT.5 Module X OUT 0 1 0 1 P2.5/Rosc 0: Input 1: Output Pad Logic
Bus Keeper P2IN.5 EN Module X IN P2IRQ.5 D P2IE.5 Q P2IFG.5 EN Set Edge Select Interrupt VCC Internal to Basic Clock Module 0
1
Interrupt Flag
P2IES.5 P2SEL.5
to DCOR CAPD.5 DC Generator
DCOR: Control Bit From Basic Clock Module If it Is Set, P2.5 Is Disconnected From P2.5 Pad DIRECTION CONTROL FROM MODULE P2DIR.5
PnSel.x P2Sel.5
PnDIR.x P2DIR.5
PnOUT.x P2OUT.5
MODULE X OUT DVSS
PnIN.x P2IN.5
MODULE X IN unused
PnIE.x P2IE.5
PnIFG.x P2IFG.5
PnIES.x P2IES.5
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43
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x P3DIR.x Direction Control From Module 0 1 Pad Logic P3OUT.x Module X OUT 0 1 P3.0/STE0 0: Input 1: Output
P3.4/UTXD0 P3.5/URXD0 P3.6/UTXD1 P3.7/URXD1
P3IN.x EN Module X IN D
x: Bit Identifier, 0 and 4 to 7 for Port P3 DIRECTION CONTROL FROM MODULE DVSS DVCC DVSS DVCC
PnSel.x P3Sel.0 P3Sel.4 P3Sel.5 P3Sel.6
PnDIR.x P3DIR.0 P3DIR.4 P3DIR.5 P3DIR.6
PnOUT.x P3OUT.0 P3OUT.4 P3OUT.5 P3OUT.6
MODULE X OUT DVSS UTXD0 DVSS UTXD1 DVSS
PnIN.x P3IN.0 P3IN.4 P3IN.5 P3IN.6 P3IN.7
MODULE X IN STE0 Unused URXD0 Unused URXD1
P3Sel.7 P3DIR.7 DVSS P3OUT.7 Output from USART0 module Output from USART1 module in x14x(1) configuration, DVSS in x13x configuration Input to USART0 module Input to USART1 module in x14x(1) configuration, unused in x13x configuration
44
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P3, P3.1, input/output with Schmitt-trigger
P3SEL.1 SYNC MM STC STE P3DIR.1 DCM_SIMO P3OUT1 (SI)MO0 From USART0 0 1 Pad Logic 0 1 P3.1/SIMO0 0: Input 1: Output
P3IN.1 EN SI(MO)0 To USART0 D
port P3, P3.2, input/output with Schmitt-trigger
P3SEL.2 SYNC MM STC STE P3DIR.2 DCM_SOMI P3OUT.2 SO(MI)0 From USART0 0 1 Pad Logic 0 1 P3.2/SOMI0 0: Input 1: Output
P3IN.2 EN (SO)MI0 To USART0 D
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45
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P3, P3.3, input/output with Schmitt-trigger
P3SEL.3 SYNC MM STC STE P3DIR.3 DCM_UCLK P3OUT.3 UCLK.0 From USART0 0 1 Pad Logic 0 1 P3.3/UCLK0 0: Input 1: Output
P3IN.3 EN UCLK0 D To USART0 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
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POST OFFICE BOX 655303
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P4, P4.0 to P4.6, input/output with Schmitt-trigger
P4SEL.x P4DIR.x Direction Control From Module Module X IN P5SEL.7 P4OUT.x Module X OUT w Pad Logic 0 1 P4.0/TB0 .. 0 1 0: Input 1: Output
P4.6/TB6
TBOUTHiZ Bus Keeper P4IN.x EN Module X IN D
x: bit identifier, 0 to 6 for Port P4 DIRECTION CONTROL FROM MODULE P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6
PnSel.x P4Sel.0 P4Sel.1 P4Sel.2 P4Sel.3 P4Sel.4 P4Sel.5 P4Sel.6 Signal from Timer_B Signal to Timer_B From P5.7
PnDIR.x P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6
PnOUT.x P4OUT.0 P4OUT.1 P4OUT.2 P4OUT.3 P4OUT.4 P4OUT.5 P4OUT.6
MODULE X OUT Out0 signal Out1 signal Out2 signal Out3 signal Out4 signal Out5 signal Out6 signal
PnIN.x P4IN.0 P4IN.1 P4IN.2 P4IN.3 P4IN.4 P4IN.5 P4IN.6
MODULE X IN CCI0A / CCI0B CCI1A / CCI1B CCI2A / CCI2B CCI3A / CCI3B CCI4A / CCI4B CCI5A / CCI5B CCI6A
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47
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P4, P4.7, input/output with Schmitt-trigger
P4SEL.7 P4DIR.7 0 1 Pad Logic P4OUT.7 DVSS 0 1 P4.7/TBCLK 0: Input 1: Output
P4IN.7 EN Timer_B, TBCLK D
port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt-trigger
P5SEL.x P5DIR.x Direction Control From Module 0 1 Pad Logic P5OUT.x Module X OUT 0 1 P5.0/STE1 0: Input 1: Output
P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH
P5IN.x EN Module X IN D
x: Bit Identifier, 0 and 4 to 7 for Port P5 PnSel.x P5Sel.0 P5Sel.4 P5Sel.5 P5Sel.6 P5Sel.7 PnDIR.x P5DIR.0 P5DIR.4 P5DIR.5 P5DIR.6 P5DIR.7 Dir. CONTROL FROM MODULE DVSS DVCC DVCC DVCC DVSS PnOUT.x P5OUT.0 P5OUT.4 P5OUT.5 P5OUT.6 P5OUT.7 MODULE X OUT DVSS MCLK SMCLK ACLK DVSS PnIN.x P5IN.0 P5IN.4 P5IN.5 P5IN.6 P5IN.7 MODULE X IN STE.1 unused unused unused TBOUTHiZ
NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7.
48
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
P5SEL.1 SYNC MM STC STE P5DIR.1 DCM_SIMO P5OUT.1 (SI)MO1 From USART1 0 1 Pad Logic 0 1 P5.1/SIMO1 0: Input 1: Output
P5IN.1 EN SI(MO)1 To USART1 D
port P5, P5.2, input/output with Schmitt-trigger
P5SEL.2 SYNC MM STC STE P5DIR.2 DCM_SOMI P5OUT.2 SO(MI)1 From USART1 0 1 Pad Logic 0 1 P5.2/SOMI1 0: Input 1: Output
P5IN.2 EN (SO)MI1 To USART1 D
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49
MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P5, P5.3, input/output with Schmitt-trigger
P5SEL.3 SYNC MM STC STE P5DIR.3 DCM_SIMO P5OUT.3 UCLK1 From USART1 0 1 Pad Logic 0 1 P5.3/UCLK1 0: Input 1: Output
P5IN.3 EN D UCLK1 To USART1 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction is always input. SPI, slave mode: The clock applied to UCLK1 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode).
50
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION input/output schematic (continued)
port P6, P6.0 to P6.7, input/output with Schmitt-trigger
P6SEL.x P6DIR.x Direction Control From Module 0 1 0 1 0: Input 1: Output Pad Logic P6.0 .. P6.7 P6OUT.x Module X OUT
Bus Keeper P6IN.x EN Module X IN D
Note: Not implemented in the MSP430x14x1 devices From ADC To ADC
x: Bit Identifier, 0 to 7 for Port P6 NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 A. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12. PnSel.x P6Sel.0 P6Sel.1 P6Sel.2 P6Sel.3 P6Sel.4 P6Sel.5 P6Sel.6 P6Sel.7 PnDIR.x P6DIR.0 P6DIR.1 P6DIR.2 P6DIR.3 P6DIR.4 P6DIR.5 P6DIR.6 P6DIR.7 DIR. CONTROL FROM MODULE P6DIR.0 P6DIR.1 P6DIR.2 P6DIR.3 P6DIR.4 P6DIR.5 P6DIR.6 P6DIR.7 PnOUT.x P6OUT.0 P6OUT.1 P6OUT.2 P6OUT.3 P6OUT.4 P6OUT.5 P6OUT.6 P6OUT.7 MODULE X OUT DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS PnIN.x P6IN.0 P6IN.1 P6IN.2 P6IN.3 P6IN.4 P6IN.5 P6IN.6 P6IN.7 MODULE X IN unused unused unused unused unused unused unused unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger
TDO Controlled by JTAG Controlled by JTAG JTAG Controlled by JTAG TDI TDO/TDI DVCC DVCC
Fuse Burn & Test Fuse Test & Emulation Module TMS TMS DVCC TCK TCK During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry DVCC TDI/TCLK
52
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MSP430x13x, MSP430x14x, MSP430x14x1 MIXED SIGNAL MICROCONTROLLER
SLAS272F - JULY 2000 - REVISED JUNE 2004
APPLICATION INFORMATION
JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 16). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition).
Time TMS Goes Low After POR TMS
ITDI/TCLK
ITF
Figure 16. Fuse Check Mode Current: MSP430F13x, MSP430F14x(1)
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
MECHANICAL DATA
MTQF006A - JANUARY 1995 - REVISED DECEMBER 1996
PAG (S-PQFP-G64)
0,50 48 33 0,27 0,17
PLASTIC QUAD FLATPACK
0,08 M
49
32
64
17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 MIN 0- 7 0,75 0,45 16
1,20 MAX
0,08 4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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1
MECHANICAL DATA
MTQF008A - JANUARY 1995 - REVISED DECEMBER 1996
PM (S-PQFP-G64)
0,27 0,17 48 33
PLASTIC QUAD FLATPACK
0,50
0,08 M
49
32
64
17 0,13 NOM
1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,45 1,35
16 Gage Plane
0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads.
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1
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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